1. Field of the Invention
The present invention relates to a semiconductor device that has an electrostatic protection diode in a signal input portion and/or a signal output portion thereof and that is accompanied by a parasitic transistor between the electrostatic protection diode and an output control transistor.
2. Description of the Prior Art
A semiconductor device that has an electrostatic protection diode in a signal input/output portion thereof is, due to its own device structure, inevitably accompanied by a parasitic transistor between the electrostatic protection diode and an output control transistor. Accordingly, in a semiconductor device having such a structure, if the parasitic transistor turns on for some cause (for example, application of an excessively high positive or negative voltage to a signal input terminal), an unintended level shift may occur in the output signal, causing inconsistency between the logic levels of the input and output signals.
The conditions under which the parasitic transistor turns on vary according to many factors such as the distance from the electrostatic protection diode to the output control transistor and the concentrations of the diffusion layers of which the individual circuit elements are formed. This makes it difficult to predict such conditions. For this reason, to overcome the above-mentioned problem, conventionally, when a semiconductor device is mounted on a circuit board, at a signal input terminal thereof is externally fitted a diode (such as a Shottky diode) of which the pn forward voltage drop VF is smaller than that of the electrostatic protection diode or that of the parasitic transistor, or alternatively a current-limiting resistor. On the other hand, the semiconductor device itself is not specially designed to cope with malfunctioning caused by the parasitic transistor, and simply its technical data includes a warning against application of an excessively high voltage or a permissible input voltage range (for example, −0.3 [V] or higher).
It is true that, even though a semiconductor device itself is not specially designed to cope with such a problem, it is possible to prevent inconsistency in the input/output logic level thereof by taking the above-mentioned measures (externally fitting a Shottky diode or a current-limiting resistor) when the semiconductor device is mounted on a circuit board, because doing so makes it difficult for the parasitic transistor to turn on.
However, taking the above-mentioned measures results in, on the side of the user of the semiconductor device, an increased number of externally fitted components, an accordingly more complicated fabrication process, a higher cost, a larger device scale, etc. Thus, the users of semiconductor devices have been strongly desiring that the semiconductor devices themselves be designed to cope with parasitic transistors.
In response to such demands, recent years have been increasingly witnessing disclosures of and proposals for semiconductor devices that are designed to cope with parasitic transistors. For example, Japanese Patent Application Laid-Open No. H10-200056 discloses a semiconductor integrated circuit device provided with a negative voltage detection circuit wherein, according to the detection signal from that circuit, the load is disconnected or the output transistor is controlled so as to prevent malfunctioning or device breakdown caused by application of a negative voltage. On the other hand, Japanese Utility Model Laid-Open No. H7-42146 discloses a bipolar IC wherein, instead of an electrostatic protection diode, a diode-connected transistor is used to prevent the parasitic transistor from turning on.